1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor, and to a method of manufacturing the same.
2. Description of the Related Art
As the integration of a semiconductor device increases, cell area has decreased and also the area available for capacitors has decreased. Thus, a method for increasing cell capacitance must be developed to manufacture a high-integrated semiconductor device.
For devices having a capacitor, e.g., a DRAM (dynamic random access memory), one way to increase cell capacitance in a smaller area is to use a dielectric layer formed with a high dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5) instead of silicon nitride or silicon oxide. A capacitor employing a tantalum oxide layer as the dielectric layer includes a first electrode and a second electrode formed of polysilicon on the dielectric layer. However, in a structure in which the Ta.sub.2 O.sub.5 layer contacts the polysilicon layer, silicon from the polysilicon layer reacts with oxygen from the tantalum oxide layer to form a silicon oxide layer on an interface between these two layers. Thus, an overall equivalent thickness to SiO.sub.2, i.e., a thickness of an effective oxide layer increases, thereby lowering capacitance, and oxygen in the tantalum oxide layer is deficient, thereby increasing leakage current.
One approach that has been used in an attempt to overcome this problem is forming the second electrode on the dielectric layer of a high dielectric constant using a single metal layer of WN or TiN.
When the second electrode is a single layer of WN, however, step coverage of the WN layer is poor. It is difficult to use the WN layer for a high-integrated semiconductor device.
When the second electrode is a single layer of TiN, a predetermined thin thickness, e.g., approximately 100 .ANG., is required to avoid increasing the leakage current density. When the TiN layer is approximately 100 .ANG., a polysilicon layer must be further formed on the TiN layer to be used as an interconnection layer. When the polysilicon layer is formed on the TiN layer, annealing after forming the polysilicon layer must be performed at 750.degree. C. or higher, e.g., 850.degree. C. Thus, the equivalent oxide thickness of the dielectric layer increases. Further, an annealing temperature of 750.degree. C. or higher is not desirable for high-integrated semiconductor devices.